Students must have prior knowledge of the concepts of BCD (binary coded decimal) and 7 segment display from their digital electronics

Students must have prior knowledge of the concepts of BCD (binary coded decimal) and 7 segment display from their digital electronics fundamentals. They also need to install a version of Quartus II simulator/compiler software, at least version 13.

MODULE OUTCOMES:

At the end of the experiment, students should gain an understanding of:

MO1:    Shift Add 3 and 7 segment display modules

MO2:    Modular design of digital systems using Verilog

INTRODUCTION

1. Binary Coded Decimal (BCD)

The binary number may be kept as pure binary, but if it is to be displayed using 7 segment display, it requires conversion to binary coded decimal (BCD). The reason is that 1 unit of 7 segment display only displays 1 digit of the decimal display that only requires 4 binary digits.

To convert binary to BCD, there is an algorithm called shift-add-3 that is commonly used. You can find information about this algorithm on the internet. The algorithm shifts the binary number to the left into groups of 4-bit BCD that correspond to digits of decimal numbers: units, tens, hundreds, etc. If the binary value in a decimal digit is 5 or more, 3 will be added to that digit only. Hence the name shift-add-3.

Even though the algorithm says shift left, but the real implementation as hardware normally does not shift – if the resources is enough. The implementation will arrange the shift-add-3 modules with bit shifted connection(miss-aligned).

2. Seven Segment Display

7 segment display is a device that displays decimal digits in 7 parts of LEDs. The display can be either common anode or common cathode. For the common anode, there is a single terminal connected to V_DD and 7 terminals to be connected to logic 0 if the LED is to be lit up, or to be connected to logic 1 if the LED is to be off; while for common cathode, there is a single terminal connected to ground and 7 terminals to be connected to logic 1 if the LED is to be lit up or to be connected to logic 0 if the LED is to be off. For this reason, the common anode is called the active low 7 segments, while the common cathode is the active high.

3. PRELAB

Use any internet resources that you can Google to construct the following:

1. The truth table of shift-add-3 module.
2. The shift-add-3 modules schematic connection to convert 9-bit binary into 3 decimal digits.
3. Schematic diagram of the common anode and common cathode 7 segment circuit connection.

SIMULATION WORKS AND EXERCISES

1.Shift-Add-3 Module

Each group is required to write the Verilog code of the shift-add-3 module either as:

1. Boolean,
2. Behavioral by if-else, or,
3. Behavioral by case

Refer to the table at the end of this document to see which mode is assigned to your group. Suggested module declaration:

module ShiftAdd3(input  [3:0] theBin,

output [3:0] theAdd3);

Declare ports as reg if necessary.

2.BCD to Seven Segment Module

Each group is required to write the Verilog code of the seven segment module either as a common anode or common cathode. Refer to the table at the end of this document to see which mode is assigned to your group. Suggested module declaration:

module BCD2to7Seg(input  [3:0] the BCD,

output [6:0] the7Seg);

Declare ports as reg if necessary.

3. 9-bit Binary to 3-digit BCD converter

Write a Verilog program to instantiate enough number of shift-add-3 modules in (1) to convert a 9-bit binary input into 3-digit BCD(units, tens, and hundreds) as you drew in Prelab (2). Suggested module declaration:

module Bin2BCD(input  [8:0] theBin,

output [3:0] unit BCS,

output [3:0] tensBCD

output [3:0] hunsBCD);

Declare ports as reg if necessary. Simulate this with the required values given in the table at the end of this document.

4. 9-bit Binary to 3-digit BCD to 7 seven segment converter

Write a Verilog code to instantiate Bin2BCD in (3) and three 7 segment modules in (2) so that we get the overall system as shown in the introduction. Suggested module declaration:

module Bin2BCDto7Seg(input  [8:0] theBin,

output [6:0] unit7Seg

output [6:0] tens7Seg

output [6:0] huns7Seg

Declare ports as reg if necessary. Simulate this with the required values given in the table at the end of this document.

DELIVERABLES

Your group has to submit the following in your report, simulation, and discussion:

1. The 4 Verilog code is requested under Simulation Work and Exercises above.
2. The timing diagram simulation snapshots of, at least, the Bin2BCD and Bin2BCDto7Seg At least simulate using the required values specific for your group. Use your imagination to add or compose more simulation values to show that you understood and learned from the lab session.
3. Discussion with regards to the code and simulation results.

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